Mathieu Maret
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4aa093034b
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Page fault: more information
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2021-10-27 17:20:28 +02:00 |
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Mathieu Maret
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1e7f99a3e2
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Correct irq asm handling
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2021-10-27 10:52:50 +02:00 |
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Mathieu Maret
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3fb667d62e
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Core exception handling w or wo err code
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2021-10-27 10:13:11 +02:00 |
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Mathieu Maret
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75dbbdb53b
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Wrap IRQ, Exception, cpu_context to be ready for user
Fix ASM where ebp was push 2 times.
One by pushw ebp
One by pushal later
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2021-10-27 00:14:22 +02:00 |
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Mathieu Maret
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8f6f6cf471
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WIP: add TSS management
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2021-10-25 21:29:18 +02:00 |
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Mathieu Maret
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5c7242e4dc
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Use ASM exception wrapper
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2021-10-08 16:42:32 +02:00 |
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Mathieu Maret
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4e14b05f72
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irq handler get complete CPU state in arguments
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2021-10-08 15:30:08 +02:00 |
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Mathieu Maret
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d2417ef349
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esp and ss are push for x86_64
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2021-10-08 12:01:57 +02:00 |
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Mathieu Maret
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ddc0c4c84a
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Wrap IRQ with ASM
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2021-10-08 11:24:02 +02:00 |
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Mathieu Maret
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4887984322
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Thinner phy page pre-booking
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2021-04-10 00:24:02 +02:00 |
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Mathieu Maret
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8c0c61c099
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Pagefault handler never come back
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2021-04-09 20:45:40 +02:00 |
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Mathieu Maret
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ede53ae4f9
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VGA renaming
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2021-01-25 14:00:06 +01:00 |
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Mathieu Maret
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bea3449b11
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Implement vsnprintf and use it
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2021-01-24 23:51:21 +01:00 |
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Mathieu Maret
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9815cc062f
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Multiple page allocation
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2020-08-28 22:40:21 +02:00 |
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Mathieu Maret
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a96fded645
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fix general purpose reg order in cpu_state
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2020-05-03 23:11:14 +02:00 |
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Mathieu Maret
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c65c7bb7b0
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More more stuff in arch subdir
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2020-04-29 23:07:01 +02:00 |
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Mathieu Maret
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e51314ffac
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organize by arch
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2020-04-27 23:45:38 +02:00 |
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