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Correct irq asm handling

This commit is contained in:
Mathieu Maret 2021-10-26 20:55:15 +02:00
parent 3fb667d62e
commit 1e7f99a3e2
1 changed files with 15 additions and 3 deletions
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18
arch/x86/irq_pit.S
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@ -7,8 +7,14 @@
.globl pit_handler
.type pit_handler, @function
pit_handler: // already got eflags, cs and eip on stack thanks to CPU
pushl $0 // err_code esp+12+8*4=44
pushal // (general reg) esp+12
pushl $0 // err_code esp+12+7*4=40
pushl %ebp
pushl %eax
pushl %ecx
pushl %edx
pushl %ebx
pushl %esi
pushl %edi
subl $2, %esp // (alignment) esp+10
pushw %ss // esp+8
pushw %ds // esp+6
@ -31,7 +37,13 @@ pit_handler: // already got eflags, cs and eip on stack thanks to CPU
popw %ds
popw %ss
addl $2,%esp
popal
popl %edi
popl %esi
popl %ebx
popl %edx
popl %ecx
popl %eax
popl %ebp
addl $4, %esp /* Ignore "error code" */
/* This restores the eflags, the cs and the eip registers */