From 1e7f99a3e209e9c33f66a5655cfc5deab28b5602 Mon Sep 17 00:00:00 2001
From: Mathieu Maret <mathieu.maret@gmail.com>
Date: Tue, 26 Oct 2021 20:55:15 +0200
Subject: [PATCH] Correct irq asm handling

---
 arch/x86/irq_pit.S | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/arch/x86/irq_pit.S b/arch/x86/irq_pit.S
index 039cb7a..4305875 100644
--- a/arch/x86/irq_pit.S
+++ b/arch/x86/irq_pit.S
@@ -7,8 +7,14 @@
 .globl pit_handler
 .type pit_handler, @function
 pit_handler:         // already got eflags, cs and eip on stack thanks to CPU 
-  pushl $0           // err_code     esp+12+8*4=44
-  pushal             // (general reg) esp+12
+  pushl $0           // err_code     esp+12+7*4=40
+  pushl %ebp
+  pushl %eax
+  pushl %ecx
+  pushl %edx
+  pushl %ebx
+  pushl %esi
+  pushl %edi
   subl $2, %esp      // (alignment)  esp+10
   pushw %ss          //              esp+8
   pushw %ds          //              esp+6
@@ -31,7 +37,13 @@ pit_handler:         // already got eflags, cs and eip on stack thanks to CPU
   popw %ds
   popw %ss
   addl $2,%esp
-  popal
+  popl %edi
+  popl %esi
+  popl %ebx
+  popl %edx
+  popl %ecx
+  popl %eax
+  popl %ebp
   addl $4, %esp /* Ignore "error code" */
 
   /* This restores the eflags, the cs and the eip registers */