306 lines
6.9 KiB
ArmAsm
306 lines
6.9 KiB
ArmAsm
/* Copyright (C) 2004 The KOS Team
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307,
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USA.
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*/
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#include "segment.h"
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.file "irq_wrappers.S"
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.text
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/** The address of the table of handlers (defined in irq.c) */
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.extern sos_irq_handler_array
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/** The address of the table of wrappers (defined below, and shared
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with irq.c */
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.globl sos_irq_wrapper_array
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/** The variable holding the nested level of the IRQ handlers */
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.extern sos_irq_nested_level_counter
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/** Update the interrupted current thread's CPU context
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Its prototype is:
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sos_thread_prepare_irq_servicing(struct sos_cpu_state *);
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*/
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.extern sos_thread_prepare_irq_servicing
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/** Update the kernel TSS in case we are switching to a thread in user
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mode in order to come back into the correct kernel stack */
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.extern sos_cpu_context_update_kernel_tss
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/** Select a thread to set on CPU (this enables user-threads
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preemption) and configure the MMU to match that of the destination
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thread.
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Its prototype is:
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struct sos_cpu_state * // Selected CPU context
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sos_thread_prepare_irq_switch_back();
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*/
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.extern sos_thread_prepare_irq_switch_back
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/* These pre-handlers are for IRQ (Master PIC) */
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.irp id, 0,1,2,3,4,5,6,7
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.p2align 2, 0x90
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sos_irq_wrapper_\id:
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.type sos_irq_wrapper_\id,@function
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/*
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* Backup the CPU context
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*/
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/* Fake error code */
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pushl $0
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/* Backup the actual context */
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pushl %ebp
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movl %esp, %ebp
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pushl %edi
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pushl %esi
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pushl %edx
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pushl %ecx
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pushl %ebx
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pushl %eax
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subl $2,%esp
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pushw %ss
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pushw %ds
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pushw %es
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pushw %fs
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pushw %gs
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/* Set correct kernel segment descriptors' value */
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movw $SOS_BUILD_SEGMENT_REG_VALUE(0, 0, SOS_SEG_KDATA), %di
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pushw %di ; popw %ds
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pushw %di ; popw %es
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pushw %di ; popw %fs
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pushw %di ; popw %gs
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/*
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* Increment IRQ nested level
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*/
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incl sos_irq_nested_level_counter
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/* Outermost IRQ only: store the interrupted context
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of the current thread */
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cmpl $1, sos_irq_nested_level_counter
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jne 1f
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pushl %esp
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call sos_thread_prepare_irq_servicing
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addl $4, %esp
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1:
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/* Send EOI to PIC. See Intel 8259 datasheet
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available on Kos website */
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movb $0x20, %al
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outb %al, $0x20
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/*
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* Call the handler with IRQ number as argument
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*/
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pushl $\id
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leal sos_irq_handler_array,%edi
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call *\id*4(%edi)
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addl $4, %esp
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/*
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* Decrement IRQ nested level
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*/
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cli /* Just in case we messed up everything in the handler */
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subl $1, sos_irq_nested_level_counter
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/* sos_irq_nested_level_counter went below 0 ?! */
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jnc 2f
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1: /* Yes: Print fatal error message */
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pushl $msg_nested_level_overflow
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call sos_display_fatal_error
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addl $4, %esp ; jmp 1b
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/* Never returns */
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2: /* No: all right ! */
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/* Was this the outermost IRQ handler ? */
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jnz 3f
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/* Yes: reschedule */
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call sos_thread_prepare_irq_switch_back
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/* Establish new context: context switch ! */
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movl %eax, %esp
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/* Prepare kernel TSS in case we are switching to a
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user thread: we make sure that we will come back
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into the kernel at a correct stack location */
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pushl %esp /* Pass the location of the context we are
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restoring to the function */
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call sos_cpu_context_update_kernel_tss
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addl $4, %esp
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3:
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/* Restore the context */
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popw %gs
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popw %fs
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popw %es
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popw %ds
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popw %ss
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addl $2,%esp
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popl %eax
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popl %ebx
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popl %ecx
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popl %edx
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popl %esi
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popl %edi
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popl %ebp
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/* Remove fake error code */
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addl $4, %esp
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iret
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.endr
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/* These pre-handlers are for IRQ (Slave PIC) */
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.irp id, 8,9,10,11,12,13,14,15
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.p2align 2, 0x90
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sos_irq_wrapper_\id:
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.type sos_irq_wrapper_\id,@function
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/*
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* Backup the CPU context
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*/
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/* Fake error code */
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pushl $0
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/* Backup the actual context */
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pushl %ebp
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movl %esp, %ebp
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pushl %edi
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pushl %esi
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pushl %edx
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pushl %ecx
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pushl %ebx
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pushl %eax
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subl $2,%esp
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pushw %ss
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pushw %ds
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pushw %es
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pushw %fs
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pushw %gs
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/* Set correct kernel segment descriptors' value */
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movw $SOS_BUILD_SEGMENT_REG_VALUE(0, 0, SOS_SEG_KDATA), %di
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pushw %di ; popw %ds
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pushw %di ; popw %es
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pushw %di ; popw %fs
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pushw %di ; popw %gs
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/*
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* Increment IRQ nested level
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*/
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incl sos_irq_nested_level_counter
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/* Outermost IRQ only: store the interrupted context
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of the current thread */
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cmpl $1, sos_irq_nested_level_counter
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jne 1f
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pushl %esp
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call sos_thread_prepare_irq_servicing
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addl $4, %esp
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1:
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/* Send EOI to PIC. See Intel 8259 datasheet
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available on Kos website */
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movb $0x20, %al
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outb %al, $0xa0
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outb %al, $0x20
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/*
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* Call the handler with IRQ number as argument
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*/
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pushl $\id
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leal sos_irq_handler_array,%edi
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call *\id*4(%edi)
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addl $4, %esp
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/*
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* Decrement IRQ nested level
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*/
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cli /* Just in case we messed up everything in the handler */
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subl $1, sos_irq_nested_level_counter
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/* sos_irq_nested_level_counter went below 0 ?! */
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jnc 2f
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1: /* Yes: Print fatal error message */
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pushl $msg_nested_level_overflow
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call sos_display_fatal_error
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addl $4, %esp ; jmp 1b
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/* Never returns */
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2: /* No: all right ! */
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/* Was this the outermost IRQ handler ? */
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jnz 3f
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/* Yes: reschedule */
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call sos_thread_prepare_irq_switch_back
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/* Establish new context: context switch ! */
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movl %eax, %esp
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/* Prepare kernel TSS in case we are switching to a
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user thread: we make sure that we will come back
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into the kernel at a correct stack location */
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pushl %esp /* Pass the location of the context we are
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restoring to the function */
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call sos_cpu_context_update_kernel_tss
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addl $4, %esp
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3:
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/* Restore the context */
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popw %gs
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popw %fs
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popw %es
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popw %ds
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popw %ss
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addl $2,%esp
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popl %eax
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popl %ebx
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popl %ecx
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popl %edx
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popl %esi
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popl %edi
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popl %ebp
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/* Remove fake error code */
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addl $4, %esp
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iret
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.endr
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.section ".rodata"
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msg_nested_level_overflow:
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.string "irq_wrappers.S: IRQ Nested level overflow ! System halted."
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/* Build the sos_irq_wrapper_array, shared with irq.c */
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.p2align 5, 0x0
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sos_irq_wrapper_array:
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.irp id, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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.long (sos_irq_wrapper_\id)
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.endr
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