187 lines
6.9 KiB
C
187 lines
6.9 KiB
C
/* Copyright (C) 2004 David Decotigny
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Copyright (C) 2003 Thomas Petazzoni
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307,
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USA.
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*/
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#include "segment.h"
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#include "gdt.h"
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/**
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* The sructure of a segment descriptor.
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*
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* @see Intel x86 doc, Vol 3, section 3.4.3, figure 3-8. For segment
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* types, see section 3.5
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*/
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struct x86_segment_descriptor
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{
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/* Lowest dword */
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sos_ui16_t limit_15_0; /* Segment limit, bits 15..0 */
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sos_ui16_t base_paged_addr_15_0; /* Base address, bits 15..0 */
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/* Highest dword */
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sos_ui8_t base_paged_addr_23_16; /* Base address bits 23..16 */
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sos_ui8_t segment_type:4; /* Section 3.4.3.1 (code/data)
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and 3.5 (system) of Intel x86 vol 3 */
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sos_ui8_t descriptor_type:1; /* 0=system, 1=Code/Data */
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sos_ui8_t dpl:2; /* Descriptor privilege level */
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sos_ui8_t present:1;
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sos_ui8_t limit_19_16:4; /* Segment limit, bits 19..16 */
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sos_ui8_t custom:1;
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sos_ui8_t zero:1;
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sos_ui8_t op_size:1; /* 0=16bits instructions, 1=32bits */
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sos_ui8_t granularity:1; /* 0=limit in bytes, 1=limit in pages */
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sos_ui8_t base_paged_addr_31_24; /* Base address bits 31..24 */
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} __attribute__ ((packed, aligned (8)));
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/**
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* The GDT register, which stores the address and size of the
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* GDT.
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*
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* @see Intel x86 doc vol 3, section 2.4, figure 2-4; and section
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* 3.5.1
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*/
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struct x86_gdt_register {
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/* The maximum GDT offset allowed to access an entry in the GDT */
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sos_ui16_t limit;
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/* This is not exactly a "virtual" address, ie an adddress such as
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those of instructions and data; this is a "linear" address, ie an
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address in the paged memory. However, in SOS we configure the
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segmented memory as a "flat" space: the 0-4GB segment-based (ie
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"virtual") addresses directly map to the 0-4GB paged memory (ie
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"linear"), so that the "linear" addresses are numerically equal
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to the "virtual" addresses: this base_addr will thus be the same
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as the address of the gdt array */
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sos_ui32_t base_addr;
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} __attribute__((packed, aligned(8)));
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/**
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* Helper macro that builds a Segment descriptor for the virtual
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* 0..4GB addresses to be mapped to the linear 0..4GB linear
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* addresses.
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*/
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#define BUILD_GDTE(descr_privilege_level,is_code) \
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((struct x86_segment_descriptor) { \
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.limit_15_0= 0xffff, \
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.base_paged_addr_15_0= 0, \
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.base_paged_addr_23_16= 0, \
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.segment_type= ((is_code)?0xb:0x3), \
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/* With descriptor_type (below) = 1 (code/data), \
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* see Figure 3-1 of section 3.4.3.1 in Intel \
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* x86 vol 3: \
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* - Code (bit 3 = 1): \
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* bit 0: 1=Accessed \
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* bit 1: 1=Readable \
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* bit 2: 0=Non-Conforming \
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* - Data (bit 3 = 0): \
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* bit 0: 1=Accessed \
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* bit 1: 1=Writable \
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* bit 2: 0=Expand up (stack-related) \
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* For Conforming/non conforming segments, see \
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* Intel x86 Vol 3 section 4.8.1.1 \
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*/ \
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.descriptor_type= 1, /* 1=Code/Data */ \
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.dpl= ((descr_privilege_level) & 0x3), \
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.present= 1, \
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.limit_19_16= 0xf, \
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.custom= 0, \
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.op_size= 1, /* 32 bits instr/data */ \
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.granularity= 1 /* limit is in 4kB Pages */ \
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})
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/** The actual GDT */
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static struct x86_segment_descriptor gdt[] = {
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[SOS_SEG_NULL] = (struct x86_segment_descriptor){ 0, },
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[SOS_SEG_KCODE] = BUILD_GDTE(0, 1),
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[SOS_SEG_KDATA] = BUILD_GDTE(0, 0),
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[SOS_SEG_UCODE] = BUILD_GDTE(3, 1),
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[SOS_SEG_UDATA] = BUILD_GDTE(3, 0),
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[SOS_SEG_KERNEL_TSS] = { 0, } /* Initialized by
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register_kernel_tss */
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};
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sos_ret_t sos_gdt_subsystem_setup(void)
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{
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struct x86_gdt_register gdtr;
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/* Address of the GDT */
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gdtr.base_addr = (sos_ui32_t) gdt;
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/* The limit is the maximum offset in bytes from the base address of
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the GDT */
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gdtr.limit = sizeof(gdt) - 1;
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/* Commit the GDT into the CPU, and update the segment
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registers. The CS register may only be updated with a long jump
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to an absolute address in the given segment (see Intel x86 doc
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vol 3, section 4.8.1). */
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asm volatile ("lgdt %0 \n\
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ljmp %1,$1f \n\
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1: \n\
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movw %2, %%ax \n\
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movw %%ax, %%ss \n\
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movw %%ax, %%ds \n\
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movw %%ax, %%es \n\
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movw %%ax, %%fs \n\
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movw %%ax, %%gs"
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:
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:"m"(gdtr),
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"i"(SOS_BUILD_SEGMENT_REG_VALUE(0, FALSE, SOS_SEG_KCODE)),
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"i"(SOS_BUILD_SEGMENT_REG_VALUE(0, FALSE, SOS_SEG_KDATA))
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:"memory","eax");
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return SOS_OK;
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}
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sos_ret_t sos_gdt_register_kernel_tss(sos_vaddr_t tss_vaddr)
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{
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sos_ui16_t regval_tss;
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/* Initialize the GDT entry */
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gdt[SOS_SEG_KERNEL_TSS]
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= (struct x86_segment_descriptor) {
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.limit_15_0= 0x67, /* See Intel x86 vol 3 section 6.2.2 */
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.base_paged_addr_15_0= (tss_vaddr) & 0xffff,
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.base_paged_addr_23_16= (tss_vaddr >> 16) & 0xff,
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.segment_type= 0x9, /* See Intel x86 vol 3 figure 6-3 */
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.descriptor_type= 0, /* (idem) */
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.dpl= 3, /* Allowed for CPL3 tasks */
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.present= 1,
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.limit_19_16= 0, /* Size of a TSS is < 2^16 ! */
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.custom= 0, /* Unused */
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.op_size= 0, /* See Intel x86 vol 3 figure 6-3 */
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.granularity= 1, /* limit is in Bytes */
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.base_paged_addr_31_24= (tss_vaddr >> 24) & 0xff
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};
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/* Load the TSS register into the processor */
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regval_tss = SOS_BUILD_SEGMENT_REG_VALUE(0, FALSE,
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SOS_SEG_KERNEL_TSS);
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asm ("ltr %0" : :"r"(regval_tss));
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return SOS_OK;
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}
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