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120 lines
2.9 KiB
120 lines
2.9 KiB
.section .text.boot |
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.global __start |
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.type __start, %function |
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// From https://developer.arm.com/docs/ddi0487/ca/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile |
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// *************************************** |
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// SCTLR_EL1, System Control Register (EL1), Page 2654 of AArch64-Reference-Manual. |
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// *************************************** |
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#define SCTLR_RESERVED (3 << 28) | (3 << 22) | (1 << 20) | (1 << 11) |
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#define SCTLR_EE_LITTLE_ENDIAN (0 << 25) |
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#define SCTLR_EOE_LITTLE_ENDIAN (0 << 24) |
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#define SCTLR_I_CACHE_DISABLED (0 << 12) |
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#define SCTLR_D_CACHE_DISABLED (0 << 2) |
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#define SCTLR_MMU_DISABLED (0 << 0) |
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#define SCTLR_MMU_ENABLED (1 << 0) |
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#define SCTLR_VALUE_MMU_DISABLED (SCTLR_RESERVED | SCTLR_EE_LITTLE_ENDIAN | SCTLR_I_CACHE_DISABLED | SCTLR_D_CACHE_DISABLED | SCTLR_MMU_DISABLED) |
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// *************************************** |
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// HCR_EL2, Hypervisor Configuration Register (EL2), Page 2487 of AArch64-Reference-Manual. |
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// *************************************** |
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#define HCR_RW (1 << 31) |
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#define HCR_VALUE HCR_RW |
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// *************************************** |
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// SCR_EL3, Secure Configuration Register (EL3), Page 2648 of AArch64-Reference-Manual. |
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// *************************************** |
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#define SCR_RESERVED (3 << 4) |
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#define SCR_RW (1 << 10) |
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#define SCR_NS (1 << 0) |
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#define SCR_VALUE (SCR_RESERVED | SCR_RW | SCR_NS) |
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// *************************************** |
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// SPSR_EL3, Saved Program Status Register (EL3) Page 389 of AArch64-Reference-Manual. |
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// *************************************** |
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#define SPSR_MASK_ALL (7 << 6) |
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#define SPSR_EL1h (5 << 0) |
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#define SPSR_VALUE (SPSR_MASK_ALL | SPSR_EL1h) |
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#define SIMD_ENABLE (3 << 20) |
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__start: |
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//Use core 0 only |
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mrs x7, mpidr_el1 |
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and x7, x7, #3 |
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cbz x7, __switch_level |
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0: wfe |
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b 0b |
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__switch_level: |
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mrs x0, CurrentEL |
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lsr x0, x0, #2 // Shift Right by 2 |
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and x0, x0, #3 |
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cmp x0, #3 |
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beq __switch_l3_l1 |
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b __switch_l2_l1 |
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__switch_l3_l1: |
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ldr x0, =SCTLR_VALUE_MMU_DISABLED |
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msr sctlr_el1, x0 |
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ldr x0, =HCR_VALUE |
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msr hcr_el2, x0 |
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ldr x0, =SCR_VALUE |
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msr scr_el3, x0 |
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ldr x0, =SPSR_VALUE |
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msr spsr_el3, x0 |
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mrs x0, CPACR_EL1 |
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and x0, x0, #SIMD_ENABLE |
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msr CPACR_EL1, x0 |
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adr x0, __start_master |
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msr elr_el3, x0 |
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eret |
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__switch_l2_l1: |
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ldr x0, =SCTLR_VALUE_MMU_DISABLED |
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msr sctlr_el1, x0 |
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ldr x0, =HCR_VALUE |
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msr hcr_el2, x0 |
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ldr x0, =SPSR_VALUE |
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msr spsr_el2, x0 |
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mrs x0, CPACR_EL1 |
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and x0, x0, #SIMD_ENABLE |
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msr CPACR_EL1, x0 |
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adr x0, __start_master |
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msr elr_el2, x0 |
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eret |
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__start_master: |
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//Setup stack pointer |
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ldr x2, = __stack_start |
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mov sp, x2 |
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//Clear BSS |
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ldr w0, = __bss_start |
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ldr w1, = __bss_size |
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1: cbz x1, 2f |
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str xzr, [x0], #8 |
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sub x1, x1, #1 |
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cbnz x1, 1b |
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2: |
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bl kernelmain |
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b 0b
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