66 lines
2.0 KiB
C
66 lines
2.0 KiB
C
#include "pic.h"
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#include "io.h"
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#include "irq.h"
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#define ICW1_ICW4 0x01 /* ICW4 (not) needed */
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#define ICW1_SINGLE 0x02 /* Single (cascade) mode */
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#define ICW1_INTERVAL4 0x04 /* Call address interval 4 (8) */
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#define ICW1_LEVEL 0x08 /* Level triggered (edge) mode */
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#define ICW1_INIT 0x10 /* Initialization - required! */
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#define ICW4_8086 0x01 /* 8086/88 (MCS-80/85) mode */
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#define ICW4_AUTO 0x02 /* Auto (normal) EOI */
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#define ICW4_BUF_SLAVE 0x08 /* Buffered mode/slave */
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#define ICW4_BUF_MASTER 0x0C /* Buffered mode/master */
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#define ICW4_SFNM 0x10 /* Special fully nested (not) */
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void initPic(void)
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{
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/* Send CMD: Init + sequence in 4 DATA */
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outb(ICW1_INIT + ICW1_ICW4, PIC_MASTER_CMD);
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outb(ICW1_INIT + ICW1_ICW4, PIC_SLAVE_CMD);
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/* Send ICW2: ctrl base address. Remap IRQ from interupt range 0x0-0xF to 0x20-0x2F as
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* intel
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* reserve interupt 0x0-0x1F in protected mode (e.g. 0-7 are CPU exception) */
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outb(IRQ_BASE_ADDRESS, PIC_MASTER_DATA);
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outb(IRQ_BASE_ADDRESS + 8, PIC_SLAVE_DATA);
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/* Send ICW3 master: mask where slaves are connected */
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outb(0x4, PIC_MASTER_DATA);
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/* Send ICW3 slave: index where the slave is connected on master */
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outb(0x2, PIC_SLAVE_DATA);
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/* Send ICW4: 8086 mode, fully nested, not buffered, no implicit EOI */
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outb(ICW4_8086, PIC_MASTER_DATA);
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outb(ICW4_8086, PIC_SLAVE_DATA);
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/* Send OCW1:
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* Closing all IRQs : waiting for a correct handler The only IRQ
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* enabled is the cascade (that's why we use 0xFB for the master) */
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outb(0xFB, PIC_MASTER_DATA);
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outb(0xFF, PIC_SLAVE_DATA);
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}
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void enableIrq(int irq)
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{
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if (irq < 8) {
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uint8_t status = inb(PIC_MASTER_DATA);
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outb((status | (1 << irq)), PIC_MASTER_DATA);
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} else {
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uint8_t status = inb(PIC_SLAVE_DATA);
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outb((status | (1 << irq)), PIC_SLAVE_DATA);
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}
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}
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void disableIrq(int irq)
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{
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if (irq < 8) {
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uint8_t status = inb(PIC_MASTER_DATA);
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outb((status & ~(1 << irq)), PIC_MASTER_DATA);
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} else {
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uint8_t status = inb(PIC_SLAVE_DATA);
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outb((status & ~(1 << irq)), PIC_SLAVE_DATA);
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}
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}
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