69 lines
1.7 KiB
C
69 lines
1.7 KiB
C
#include "idt.h"
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static struct idtEntry idt[IDT_NUM];
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int idtSetup()
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{
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struct idtRegister idtr;
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for (int i = 0; i < IDT_NUM; i++) {
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struct idtEntry *idte = idt + i;
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/* Setup an empty IDTE interrupt gate, see figure 5-2 in Intel
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x86 doc, vol 3 */
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idte->seg_sel = BUILD_SEGMENT_SELECTOR(RING_0, 0, SEGMENT_IDX_CODE);
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idte->reserved = 0;
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idte->flags = 0;
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idte->type = 0x6; /* Interrupt gate (110b) */
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idte->op_size = 1; /* 32bits instructions */
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/* Disabled it for now */
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idte->zero = 0;
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idte->offset_low = 0;
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idte->offset_high = 0;
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idte->dpl = 0;
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idte->present = 0;
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}
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/*
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* Setup the IDT register, see Intel x86 doc vol 3, section 5.8.
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*/
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/* Address of the IDT */
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idtr.base_addr = (uint32_t)idt;
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/* The limit is the maximum offset in bytes from the base address of
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the IDT */
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idtr.limit = sizeof(idt) - 1;
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/* Commit the IDT into the CPU */
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asm volatile("lidt %0\n" ::"m"(idtr) : "memory");
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return 0;
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}
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int idt_set_handler(int index, unsigned int addr, int priviledge)
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{
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struct idtEntry *idte;
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if (index < 0 || index >= IDT_NUM)
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return -1;
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if ((priviledge < 0) || priviledge > 3)
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return -1;
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idte = idt + index;
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if (addr != (unsigned int)NULL) {
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idte->offset_low = addr & 0xffff;
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idte->offset_high = (addr >> 16) & 0xffff;
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idte->dpl = priviledge;
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idte->present = 1;
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} else {
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idte->offset_low = 0;
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idte->offset_high = 0;
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idte->dpl = 0;
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idte->present = 0;
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}
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return 0;
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}
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