195 lines
6.2 KiB
C
195 lines
6.2 KiB
C
#include "klibc.h"
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#include "errno.h"
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#include "mem.h"
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#include "paging.h"
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#include "stdarg.h"
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#include "vga.h"
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// In a Vaddr, 10 first bit (MSB) are the index in the Page Directory. A Page Directory Entry point to a Page Table.
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// The 10 next bits are then an index in this Page Table. A Page Table Entry then point to a physical address at which is added the remaining 12 bits.
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// So they are 1024 entry in the PD, each of them pointing to a PT of 1024 entry. Each PTE pointing to 4K page.
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// First address (up to page_desc from mem.c) are mapped such as Paddr == Vaddr.
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// To make PD always accessible a (x86?) trick is used : The mirroring. A given entry N in the PD point to the PD (this is possible because PDE very looks like PTE in x86).
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// So N << (10 + 12 = 4Mo) point to the Paddr of PD. Then, accessing N * 4Mo + I * 4Ko is accessing the PT of the Ieme entry in the PD (as MMU take the PD pointed by the PDE number N like a PT).
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// More particularly, accessing N * 4Mo + N * 4ko is accessing the PD.
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//
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// PD is at Vaddr N * 4Mo and take 4ko. Each PT are allocated dynamically.
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// Just make sure that N have not been used by identity mapping
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#define PT_SHIFT 12
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#define PTE_MASK 0x3ff //10bits
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#define PD_SHIFT 22
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#define PD_MIRROR_PAGE_IDX 1023
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struct pde {
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uint32_t present : 1;
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uint32_t write : 1; // 0 read - 1 RW
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uint32_t user : 1; // 0 supervisor - 1 user
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uint32_t write_through : 1; // 0 write-back - 1 write_through
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uint32_t cache_disable : 1;
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uint32_t access : 1; // have been accessed
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uint32_t zero : 1; // Not used
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uint32_t size : 1; // 0 for 4Kb 1 for 4Mb
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uint32_t ignored : 1;
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uint32_t available : 3;
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uint32_t pt_addr : 20;
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} __attribute__((packed));
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struct pte {
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uint32_t present : 1;
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uint32_t write : 1; // 0 read - 1 RW
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uint32_t user : 1; // 0 supervisor - 1 user
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uint32_t write_through : 1; // 0 write-back - 1 write_through
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uint32_t cache_disable : 1;
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uint32_t access : 1; // have been accessed
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uint32_t dirty : 1; // if set, indicates that page has been written to. This flag is
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// not updated by the CPU, and once set will not unset itself.
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uint32_t zero : 1; // if PAT is supported, shall indicate the memory type. Otherwise,
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// it must be 0.
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uint32_t global : 1; // if set, prevents the TLB from updating the address in its cache
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// if CR3 is reset. Note, that the page global enable bit in CR4
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// must be set to enable this feature.
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uint32_t available : 3;
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uint32_t paddr : 20;
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} __attribute__((packed));
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struct pdbr {
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uint32_t zero1 : 3; // reserved
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uint32_t write_through : 1; // 0 write-back - 1 write-through
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uint32_t cache_disabled : 1; // 1=cache disabled
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uint32_t zero2 : 7; // reserved
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uint32_t pd_paddr : 20;
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} __attribute__((packed));
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// invalidate the TLB entry for the page located at the given virtual address
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static inline void __native_flush_tlb_single(unsigned long addr)
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{
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asm volatile("invlpg (%0)" ::"r"(addr) : "memory");
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}
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int pagingSetup(paddr_t upperKernelAddr)
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{
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struct pdbr cr3;
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// x86 got 1024 of pde for 4Byte each: 4ko !
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struct pde *pd = (struct pde *)allocPhyPage();
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memset(pd, 0, PAGE_SIZE);
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memset(&cr3, 0x0, sizeof(struct pdbr));
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cr3.pd_paddr = ((paddr_t)pd) >> 12;
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// MMU not enabled for the moment. No need to use mirroring
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// Identity mapping up to upperKernelAddr
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for (paddr_t i = 0; i < upperKernelAddr; i += PAGE_SIZE) {
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uint pdEntry = i >> (PD_SHIFT);
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uint ptEntry = (i >> PT_SHIFT ) & PTE_MASK;
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struct pte *pt;
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if (pd[pdEntry].present){
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pt = (struct pte *)(pd[pdEntry].pt_addr << PT_SHIFT);
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refPhyPage((paddr_t)pt);
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} else {
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pt = (struct pte *)allocPhyPage();
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memset(pt, 0, PAGE_SIZE);
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pd[pdEntry].present = 1;
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pd[pdEntry].write = 1;
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pd[pdEntry].pt_addr = ((paddr_t)pt >> PT_SHIFT);
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}
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pt[ptEntry].present = 1;
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pt[ptEntry].write = 1; //TODO set Kernel code as RO
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pt[ptEntry].paddr = i >> PAGE_SHIFT;
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}
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// Setup mirroring
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pd[PD_MIRROR_PAGE_IDX].present = 1;
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pd[PD_MIRROR_PAGE_IDX].write = 1;
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pd[PD_MIRROR_PAGE_IDX].pt_addr = ((paddr_t)pd >> PT_SHIFT);
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// Loading of the PDBR in the MMU:
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asm volatile ("movl %0,%%cr3\n\t"
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"movl %%cr0,%%eax\n\t"
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"orl $0x80010000, %%eax\n\t" /* bit 31 | bit 16 */
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"movl %%eax,%%cr0\n\t"
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"jmp 1f\n\t"
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"1:\n\t"
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"movl $2f, %%eax\n\t"
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"jmp *%%eax\n\t"
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"2:\n\t" ::"r"(cr3):"memory","eax");
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return 0;
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}
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int pageMap(vaddr_t vaddr, paddr_t paddr, int flags)
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{
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uint pdEntry = vaddr >> (PD_SHIFT);
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uint ptEntry = (vaddr >> PT_SHIFT) & PTE_MASK;
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// Thank to mirroring, we can access the PD
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struct pde *pd = (struct pde *)(PD_MIRROR_PAGE_IDX * (1U << 22) +
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PD_MIRROR_PAGE_IDX * (1U << 12));
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struct pte *pt = (struct pte *)(PD_MIRROR_PAGE_IDX * (1U << 22) +
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pdEntry * (1U << 12));
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if(!pd[pdEntry].present){
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paddr_t ptPhy = allocPhyPage();
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memset((void *)ptPhy, 0, PAGE_SIZE);
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pd[pdEntry].user = (flags & PAGING_MEM_USER) ? 0:1;
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pd[pdEntry].present = 1;
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pd[pdEntry].write = 1;
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pd[pdEntry].pt_addr = (ptPhy >> PT_SHIFT);
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__native_flush_tlb_single((vaddr_t)pt);
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}
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// Already mapped ? Remove old mapping
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if (pt[ptEntry].present) {
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unrefPhyPage(pt[ptEntry].paddr << PAGE_SHIFT);
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} // PTE not already used ? We will use it ! So increase the PT ref count
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else {
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refPhyPage(pd[pdEntry].pt_addr << PAGE_SHIFT);
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}
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pt[ptEntry].user = (flags & PAGING_MEM_USER) ? 0 : 1;
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pt[ptEntry].present = 1;
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pt[ptEntry].write = (flags & PAGING_MEM_WRITE) ? 0 : 1;
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pt[ptEntry].paddr = paddr >> PAGE_SHIFT;
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refPhyPage(paddr);
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__native_flush_tlb_single(vaddr);
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return 0;
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}
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int pageUnmap(vaddr_t vaddr)
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{
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uint pdEntry = vaddr >> (PD_SHIFT);
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uint ptEntry = (vaddr >> PT_SHIFT) & PTE_MASK;
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// Thank to mirroring, we can access the PD
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struct pde *pd =
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(struct pde *)(PD_MIRROR_PAGE_IDX * (1U << 22) + PD_MIRROR_PAGE_IDX * (1U << 12));
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struct pte *pt =
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(struct pte *)(PD_MIRROR_PAGE_IDX * (1U << 22) + pdEntry * (1U << 12));
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if (!pd[pdEntry].present)
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return -EINVAL;
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if (!pt[ptEntry].present)
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return -EINVAL;
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unrefPhyPage(pt[ptEntry].paddr << PAGE_SHIFT);
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pt[ptEntry].present = 0;
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// PTE not used. Decrease refcount on it. Is PT not used anymore ?
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if(unrefPhyPage(pd[pdEntry].pt_addr<< PT_SHIFT) == 0){
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pd[pdEntry].present = 0;
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__native_flush_tlb_single((vaddr_t)pt);
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}
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__native_flush_tlb_single(vaddr);
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return 0;
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}
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