#define ASM_SOURCE
#include "segment.h"

.file "syscall_wrappers.S"

.text

/* The address of the real "C" syscall function */
.extern syscallExecute

/** Update the kernel TSS in case we are switching to a thread in user
	mode in order to come back into the correct kernel stack */
.extern cpu_context_update_kernel_tss

/* The address of the function to call to set back the user thread's
   MMU configuration upon return to user context */
.extern threadPrepareSyscallSwitchBack

.p2align 2, 0x90
.globl syscallHandler
syscallHandler:
.type syscallHandler,@function
 
  /* Fake error code */
  pushl $0
  /* Backup the context */
  pushl %ebp
  movl %esp, %ebp
 
  pushl %eax
  pushl %ecx
  pushl %edx
  pushl %ebx
  pushl %esi
  pushl %edi
  subl  $2,%esp
  pushw %ss
  pushw %ds
  pushw %es
  pushw %fs
  pushw %gs

  /* Set correct kernel segment descriptors' value */
  movw $BUILD_SEGMENT_REG_VALUE(0, 0, SEG_KDATA), %di
  pushw %di ; popw %ds
  pushw %di ; popw %es
  pushw %di ; popw %fs
  pushw %di ; popw %gs

  /* Prepare the call to do_syscall */ 
  pushl %esp /* user_ctxt */
  pushl %eax /* syscall ID */

  call  syscallExecute
  /* Unallocate the stack used by the
     do_syscall arguments */
  addl  $8, %esp

  /* store the do_syscall return value into interrupted context */
  movl %eax, 32(%esp)

  /* Set the MMU configuration to that of the user thread's process */
  pushl %esp /* user_ctxt */
  call threadPrepareSyscallSwitchBack
  addl  $4, %esp /* Unallocate the stack */

  /* Prepare kernel TSS because we are switching back to a user
     thread: we make sure that we will come back into the kernel at a
     correct stack location */
  pushl %esp /* Pass the location of the context we are
  	        restoring to the function */
  call cpu_context_update_kernel_tss
  addl $4, %esp

  /* Restore the user context */
  popw  %gs
  popw  %fs
  popw  %es
  popw  %ds
  popw  %ss
  addl  $2,%esp
  popl %edi
  popl %esi
  popl %ebx
  popl %edx
  popl %ecx
  popl %eax
  popl  %ebp
  /* Remove fake error code */
  addl $4, %esp
  iret