Add count for allocated and mapped page
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56a16b9ea5
commit
4bbe08d8f5
16
core/mem.c
16
core/mem.c
@ -9,7 +9,9 @@ static struct mem_desc *used_page;
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static unsigned long bottom_mem;
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static unsigned long top_mem;
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int memSetup(paddr_t upperMem, paddr_t * lastUsedOut)
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static unsigned long allocatedPage = 0;
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int memSetup(paddr_t upperMem, paddr_t *lastUsedOut)
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{
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// Align upper mem (in kB) on page size even if it does loose a page
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upperMem = ALIGN_DOWN(upperMem, PAGE_SIZE / 1024);
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@ -22,9 +24,9 @@ int memSetup(paddr_t upperMem, paddr_t * lastUsedOut)
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uint lastUsed = (memdesc_end >> PAGE_SHIFT) + 1;
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list_init(free_page);
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list_init(used_page);
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bottom_mem = lastUsed;
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bottom_mem = lastUsed;
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*lastUsedOut = memdesc_end;
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top_mem = upperMem * 1024;
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top_mem = upperMem * 1024;
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for (uint i = 0; i < (upperMem / (PAGE_SIZE / 1024)); i++) {
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struct mem_desc *mem = &page_desc[i];
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if (i < lastUsed) {
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@ -56,6 +58,7 @@ paddr_t allocPhyPage(void)
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struct mem_desc *mem = list_pop_head(free_page);
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mem->ref = 1;
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list_add_tail(used_page, mem);
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allocatedPage++;
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return mem->phy_addr;
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}
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@ -67,6 +70,7 @@ int unrefPhyPage(paddr_t addr)
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}
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mem->ref--;
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if (mem->ref == 0) {
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allocatedPage--;
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list_delete(used_page, mem);
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list_add_tail(free_page, mem);
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}
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@ -82,9 +86,15 @@ int refPhyPage(paddr_t addr)
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}
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mem->ref++;
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if (mem->ref == 1) {
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allocatedPage++;
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list_add_tail(used_page, mem);
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list_delete(free_page, mem);
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}
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return 0;
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}
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unsigned long getNbAllocatedPage(void)
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{
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return allocatedPage;
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}
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@ -21,3 +21,4 @@ int memSetup(paddr_t upperMem, paddr_t *lastUsed);
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paddr_t allocPhyPage(void);
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int unrefPhyPage(paddr_t addr);
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int refPhyPage(paddr_t addr);
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unsigned long getNbAllocatedPage(void);
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@ -1,26 +1,31 @@
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#include "klibc.h"
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#include "errno.h"
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#include "mem.h"
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#include "paging.h"
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#include "errno.h"
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#include "klibc.h"
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#include "mem.h"
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#include "stdarg.h"
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#include "vga.h"
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// In a Vaddr, 10 first bit (MSB) are the index in the Page Directory. A Page Directory Entry point to a Page Table.
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// The 10 next bits are then an index in this Page Table. A Page Table Entry then point to a physical address at which is added the remaining 12 bits.
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// So they are 1024 entry in the PD, each of them pointing to a PT of 1024 entry. Each PTE pointing to 4K page.
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// First address (up to page_desc from mem.c) are mapped such as Paddr == Vaddr.
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// To make PD always accessible a (x86?) trick is used : The mirroring. A given entry N in the PD point to the PD (this is possible because PDE very looks like PTE in x86).
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// So N << (10 + 12 = 4Mo) point to the Paddr of PD. Then, accessing N * 4Mo + I * 4Ko is accessing the PT of the Ieme entry in the PD (as MMU take the PD pointed by the PDE number N like a PT).
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// More particularly, accessing N * 4Mo + N * 4ko is accessing the PD.
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// In a Vaddr, 10 first bit (MSB) are the index in the Page Directory. A Page Directory Entry
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// point to a Page Table. The 10 next bits are then an index in this Page Table. A Page Table
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// Entry then point to a physical address at which is added the remaining 12 bits. So they are
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// 1024 entry in the PD, each of them pointing to a PT of 1024 entry. Each PTE pointing to 4K
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// page. First address (up to page_desc from mem.c) are mapped such as Paddr == Vaddr. To make
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// PD always accessible a (x86?) trick is used : The mirroring. A given entry N in the PD point
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// to the PD (this is possible because PDE very looks like PTE in x86). So N << (10 + 12 = 4Mo)
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// point to the Paddr of PD. Then, accessing N * 4Mo + I * 4Ko is accessing the PT of the Ieme
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// entry in the PD (as MMU take the PD pointed by the PDE number N like a PT). More
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// particularly, accessing N * 4Mo + N * 4ko is accessing the PD.
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//
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// PD is at Vaddr N * 4Mo and take 4ko. Each PT are allocated dynamically.
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// Just make sure that N have not been used by identity mapping
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#define PT_SHIFT 12
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#define PTE_MASK 0x3ff //10bits
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#define PTE_MASK 0x3ff // 10bits
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#define PD_SHIFT 22
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#define PD_MIRROR_PAGE_IDX 1023U
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static unsigned long mappedPage = 0;
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struct pde {
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uint32_t present : 1;
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uint32_t write : 1; // 0 read - 1 RW
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@ -61,7 +66,6 @@ struct pdbr {
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uint32_t pd_paddr : 20;
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} __attribute__((packed));
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// invalidate the TLB entry for the page located at the given virtual address
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static inline void __native_flush_tlb_single(unsigned long addr)
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{
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@ -84,9 +88,9 @@ int pagingSetup(paddr_t upperKernelAddr)
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// Identity mapping up to upperKernelAddr
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for (paddr_t i = 0; i < upperKernelAddr; i += PAGE_SIZE) {
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uint pdEntry = i >> (PD_SHIFT);
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uint ptEntry = (i >> PT_SHIFT ) & PTE_MASK;
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uint ptEntry = (i >> PT_SHIFT) & PTE_MASK;
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struct pte *pt;
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if (pd[pdEntry].present){
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if (pd[pdEntry].present) {
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pt = (struct pte *)(pd[pdEntry].pt_addr << PT_SHIFT);
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refPhyPage((paddr_t)pt);
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} else {
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@ -94,31 +98,31 @@ int pagingSetup(paddr_t upperKernelAddr)
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memset(pt, 0, PAGE_SIZE);
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pd[pdEntry].present = 1;
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pd[pdEntry].write = 1;
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pd[pdEntry].pt_addr = ((paddr_t)pt >> PT_SHIFT);
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pd[pdEntry].write = 1;
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pd[pdEntry].pt_addr = ((paddr_t)pt >> PT_SHIFT);
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}
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pt[ptEntry].present = 1;
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pt[ptEntry].write = 1; //TODO set Kernel code as RO
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pt[ptEntry].write = 1; // TODO set Kernel code as RO
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pt[ptEntry].paddr = i >> PAGE_SHIFT;
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}
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// Setup mirroring
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pd[PD_MIRROR_PAGE_IDX].present = 1;
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pd[PD_MIRROR_PAGE_IDX].write = 1;
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pd[PD_MIRROR_PAGE_IDX].write = 1;
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pd[PD_MIRROR_PAGE_IDX].pt_addr = ((paddr_t)pd >> PT_SHIFT);
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// Loading of the PDBR in the MMU:
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asm volatile ("movl %0,%%cr3\n\t"
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"movl %%cr0,%%eax\n\t"
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"orl $0x80010000, %%eax\n\t" /* bit 31 | bit 16 */
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"movl %%eax,%%cr0\n\t"
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"jmp 1f\n\t"
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"1:\n\t"
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"movl $2f, %%eax\n\t"
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"jmp *%%eax\n\t"
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"2:\n\t" ::"r"(cr3):"memory","eax");
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asm volatile("movl %0,%%cr3\n\t"
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"movl %%cr0,%%eax\n\t"
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"orl $0x80010000, %%eax\n\t" /* bit 31 | bit 16 */
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"movl %%eax,%%cr0\n\t"
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"jmp 1f\n\t"
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"1:\n\t"
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"movl $2f, %%eax\n\t"
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"jmp *%%eax\n\t"
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"2:\n\t" ::"r"(cr3)
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: "memory", "eax");
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return 0;
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}
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@ -128,19 +132,20 @@ int pageMap(vaddr_t vaddr, paddr_t paddr, int flags)
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uint ptEntry = (vaddr >> PT_SHIFT) & PTE_MASK;
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// Thank to mirroring, we can access the PD
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struct pde *pd =
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(struct pde *)((PD_MIRROR_PAGE_IDX << 22) + (PD_MIRROR_PAGE_IDX << 12));
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struct pde *pd = (struct pde *)((PD_MIRROR_PAGE_IDX << PD_SHIFT) +
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(PD_MIRROR_PAGE_IDX << PT_SHIFT));
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struct pte *pt = (struct pte *)((PD_MIRROR_PAGE_IDX << 22) + (pdEntry << 12));
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struct pte *pt =
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(struct pte *)((PD_MIRROR_PAGE_IDX << PD_SHIFT) + (pdEntry << PT_SHIFT));
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if (!pd[pdEntry].present) {
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paddr_t ptPhy = allocPhyPage();
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if (ptPhy == (vaddr_t)NULL)
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return ENOMEM;
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pd[pdEntry].user = (flags & PAGING_MEM_USER) ? 1:0;
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pd[pdEntry].user = (flags & PAGING_MEM_USER) ? 1 : 0;
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pd[pdEntry].present = 1;
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pd[pdEntry].write = 1;
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pd[pdEntry].write = 1;
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pd[pdEntry].pt_addr = (ptPhy >> PT_SHIFT);
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__native_flush_tlb_single((vaddr_t)pt);
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@ -162,6 +167,7 @@ int pageMap(vaddr_t vaddr, paddr_t paddr, int flags)
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refPhyPage(paddr);
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__native_flush_tlb_single(vaddr);
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mappedPage++;
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return 0;
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}
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@ -171,11 +177,11 @@ int pageUnmap(vaddr_t vaddr)
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uint ptEntry = (vaddr >> PT_SHIFT) & PTE_MASK;
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// Thank to mirroring, we can access the PD
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struct pde *pd =
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(struct pde *)(PD_MIRROR_PAGE_IDX * (1U << 22) + PD_MIRROR_PAGE_IDX * (1U << 12));
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struct pde *pd = (struct pde *)((PD_MIRROR_PAGE_IDX << PD_SHIFT) +
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(PD_MIRROR_PAGE_IDX << PT_SHIFT));
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struct pte *pt =
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(struct pte *)(PD_MIRROR_PAGE_IDX * (1U << 22) + pdEntry * (1U << 12));
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(struct pte *)((PD_MIRROR_PAGE_IDX << PD_SHIFT) + (pdEntry << PT_SHIFT));
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if (!pd[pdEntry].present)
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return -EINVAL;
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if (!pt[ptEntry].present)
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@ -185,11 +191,16 @@ int pageUnmap(vaddr_t vaddr)
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pt[ptEntry].present = 0;
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// PTE not used. Decrease refcount on it. Is PT not used anymore ?
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if(unrefPhyPage(pd[pdEntry].pt_addr<< PT_SHIFT) == 0){
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if (unrefPhyPage(pd[pdEntry].pt_addr << PT_SHIFT) == 0) {
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pd[pdEntry].present = 0;
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__native_flush_tlb_single((vaddr_t)pt);
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}
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__native_flush_tlb_single(vaddr);
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mappedPage--;
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return 0;
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}
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unsigned long getNbMappedPage(void)
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{
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return mappedPage;
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}
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@ -9,3 +9,4 @@ int pagingSetup(paddr_t upperKernelAddr);
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int pageMap(vaddr_t vaddr, paddr_t paddr, int flags);
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int pageUnmap(vaddr_t vaddr);
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unsigned long getNbMappedPage(void);
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