mathieu/matos
1
1
Fork 0
Code Issues Pull Requests Releases Wiki Activity

esp and ss are push for x86_64

Browse Source
This commit is contained in:
Mathieu Maret 2021-10-07 21:53:25 +02:00
parent ddc0c4c84a
commit d2417ef349
2 changed files with 50 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/x86/interrupt.h
View File

@ -6,9 +6,7 @@ struct interrupt_frame {
uint32_t eip;
uint32_t cs;
uint32_t eflags;
uint32_t esp;
uint32_t ss;
};
} __attribute__((packed));
// Exception
#define DECLARE_INTERRUPT(int_nb) \

49
arch/x86/irq_wrappers.S Normal file
View File

@ -0,0 +1,49 @@
#define ASM_SOURCE 1
.file "irq_wrappers.S"
.text
.extern interrupt_handler_pic
.globl irq_handler_wrapper_array
.altmacro
.macro interrupt_pic irq
int_wrapper_\irq:
.type int_wrapper_\irq,@function
/* INTERRUPT FRAME START */
/* ALREADY PUSHED TO US BY THE PROCESSOR UPON ENTRY TO THIS INTERRUPT */
/* uint32_t ip */
/* uint32_t cs; */
/* uint32_t flags */
/* uint32_t sp; */
/* uint32_t ss; */
/* Pushes the general purpose registers to the stack */
pushal
/* Interrupt frame end */
pushl %esp
pushl $\irq
call interrupt_handler_pic
addl $8, %esp
popal
iret
.endm
.set i, 0
.rept 0x10
interrupt_pic %i
.set i, i+1
.endr
.macro ref_int_wrapper irq
.long int_wrapper_\irq
.endm
.section ".rodata"
.p2align 5, 0x0
irq_handler_wrapper_array:
.set i, 0x0
.rept 0x10
ref_int_wrapper %i
.set i, i+1
.endr