2021-10-07 21:53:25 +02:00
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#define ASM_SOURCE 1
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.file "irq_wrappers.S"
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.text
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.extern interrupt_handler_pic
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.globl irq_handler_wrapper_array
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.altmacro
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.macro interrupt_pic irq
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int_wrapper_\irq:
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.type int_wrapper_\irq,@function
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/* INTERRUPT FRAME START */
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/* ALREADY PUSHED TO US BY THE PROCESSOR UPON ENTRY TO THIS INTERRUPT */
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/* uint32_t ip */
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/* uint32_t cs; */
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/* uint32_t flags */
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2021-10-07 23:11:17 +02:00
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/* Pushes the other reg to save same and look like a struct cpu_state*/
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/* Fake error code */
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pushl $0
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/* Backup the actual context */
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pushl %ebp
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movl %esp, %ebp
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pushl %edi
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pushl %esi
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pushl %edx
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pushl %ecx
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pushl %ebx
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pushl %eax
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subl $2,%esp
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pushw %ss
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pushw %ds
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pushw %es
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pushw %fs
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pushw %gs
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push %esp
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2021-10-07 21:53:25 +02:00
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pushl $\irq
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call interrupt_handler_pic
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addl $8, %esp
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2021-10-07 23:11:17 +02:00
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/* Restore the context */
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popw %gs
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popw %fs
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popw %es
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popw %ds
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popw %ss
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addl $2,%esp
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popl %eax
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popl %ebx
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popl %ecx
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popl %edx
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popl %esi
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popl %edi
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popl %ebp
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/* Remove fake error code */
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addl $4, %esp
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2021-10-07 21:53:25 +02:00
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iret
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.endm
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2021-10-07 23:11:17 +02:00
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2021-10-07 21:53:25 +02:00
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.set i, 0
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.rept 0x10
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interrupt_pic %i
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.set i, i+1
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.endr
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.macro ref_int_wrapper irq
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.long int_wrapper_\irq
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.endm
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.section ".rodata"
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.p2align 5, 0x0
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irq_handler_wrapper_array:
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.set i, 0x0
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.rept 0x10
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ref_int_wrapper %i
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.set i, i+1
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.endr
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